The invention relates to data bus communication schemes and in particular, to a bi-directional bus level translator for connecting between data buses operating at different supply voltages.
A 2-wire bi-directional data bus, such as the Inter-Integrated Circuit (I2C) data bus, is commonly used for communication between integrated circuit (IC) devices. Sometimes, a data bus must connect IC devices that are operating on different supply voltages. Thus, there is a need to provide fully bi-directional data transfer between a bus section that operates at a higher voltage and a bus section that operates at a lower voltage.
An I2C two-way data bus is normally pulled up to a positive supply voltage (xe2x80x9cthe bus voltagexe2x80x9d) by passive pull-up devices and relies on pull-down devices at the IC devices connected to the data bus to switch the voltage level on the bus for data transfer. FIG. 1 is a schematic diagram of a bi-directional data bus system operating based on the principles of the I2C standard and including two bus sections operating at different bus voltages. In FIG. 1, data bus system 10 includes a bus section BUS-A operating at a bus voltage VA and a bus section BUS-B operating at a bus voltage VB. IC devices operating on a supply voltage of VA are connected to bus section BUS-A and IC devices operating on a supply voltage of VB are connected to bus section BUS-B.
Each bus section is connected to the respective positive supply voltage (VA or VB) by a passive pull-up device, such as a resistor. Thus, when the data bus is free, the bus sections are at a logical HIGH level. When data is to be transferred on the data bus, output drivers of the IC devices connected to the data bus operate to pull-down the voltage on the data bus. Under the I2C standard, the output drivers of IC devices connected to the data bus must have an open-drain or open-collector pull-down device. As shown in FIG. 1, an open-drain pull-down transistor PD1, belonging to an output driver circuit of an IC device, is connected to bus section BUS-A and an open-drain pull-down transistor PD2, belonging to an output driver circuit of another IC device, is connected to bus section BUS-B.
When the two bus sections are operating at different bus voltages, some means of isolating IC devices connected to the bus and transferring the logic voltage levels between the bus sections is required. For example, an IC operating at 3.3 volts may need to communicate with another IC connected to the same data bus system and operating at 5.0 volts. U.S. Pat. No. 5,689,196 to Schutte describes an approach which uses a single transistor, such as a field effect transistor, to connect two bus sections with dissimilar voltages. FIG. 1 illustrates the use of the bi-directional level shifting approach described by Schutte in data bus system 10 for connecting bus sections with different supply voltages. In FIG. 1, a single N-channel enhancement MOS transistor 12 connects bus section BUS-A and bus section BUS-B. The gate terminal of transistor 12 is driven by the lower of the two bus voltages which is assumed to be bus voltage VA. It can be seen that logic levels can be transferred in both directions of the data bus, independent of the supply voltages of the bus sections.
Although the bi-directional level shifting scheme described by Schutte is simple and works well, it imposes an additional requirement for the output drivers of IC devices connected to the data bus. Specifically, because the pull-down devices in the output drivers now have to drive an additional series resistance present by transistor 12, the pull-down devices must be substantially oversized to meet the pull-down requirements of the data bus system. For an I2C data bus system, the pull-down devices must be sized larger than the requirement of the I2C specification.
A more significant limitation of the bi-directional level shifting scheme described by Schutte is that it imposes a design constraint on IC devices to be connected to the data bus. IC designers must have a priori information regarding the additional drive requirement of the pull-down devices or the IC devices may not be designed with sufficient pull-down capabilities to drive the level-shifting FET. In the case of the I2C data bus system, a whole class of IC devices built to meet the minimum requirement of the I2C specification may not be able to work in a mix voltage data bus system utilizing the bi-directional level shifting scheme described by Schutte.
Therefore, an improved scheme for bi-directional level shifting on a data bus is desired.
According to one embodiment of the present invention, a circuit is provided to transfer data between a first data bus section operating on a first supply voltage and a second data bus section operating on a second supply voltage different from the first supply voltage. The circuit includes a first circuit path coupled to receive a data signal from the first data bus section and to drive the second data bus section and a second circuit path coupled to receive a data signal from the second data bus section and to drive the first data bus section. Each of the first and second circuit paths includes a delay circuit, a flip flop, a logic circuit providing an AND function and an output driver circuit.
The delay circuit is coupled to receive the respective data signal and to provide a first signal corresponding to the respective data signal, the delay circuit introducing a predetermined delay to the data signal only when the data signal has a first logical value. The flip flop includes a data input terminal, a data output terminal, an inverse data output terminal, a clock input terminal receiving the first signal, and a reset terminal receiving an inverse of the respective data signal. The data input terminal of the flip flop in one of the first and second circuit paths is coupled to the inverse data output terminal of the flip flop in the other one of the first and second circuit paths. The logic circuit providing an AND function, such as an AND gate, includes a first input terminal coupled to the data output terminal of the flip flop, a second input terminal coupled to the data input terminal of the flip flop, and an output terminal providing an output driver signal. Finally, the output driver circuit is coupled to drive the respective data bus section in response to the output driver signal.
In operation, when the data signal received on one of the first and second data bus sections has the first logical value, the output driver signal of the respective circuit path is asserted and the output driver circuit drives the other one of the first and second data bus sections to the first logical value in response to the output driver signal.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.